The present invention relates to semiconductor memory cells including a memory element formed by a field effect transistor having a gate insulating film made of a ferroelectric film, and semiconductor memory devices having semiconductor memory cells arranged in an array.
Nonvolatile memories using a ferroelectric material are roughly divided into two types, namely a capacitor type and a field effect transistor (FET) type having a gate insulating film made of a ferroelectric film.
The capacitor type ferroelectric memories have a structure similar to that of dynamic random access memories (DRAMs). The capacitor type ferroelectric memories hold charge in a ferroelectric capacitor, and distinguish between “0” and “1” of information according to the polarization direction of the ferroelectric material. The polarization accumulated in the ferroelectric capacitor is coupled with charge that is induced by electrodes respectively located above and below the polarization, and does not disappear in the state where the voltage is cut off. However, when reading information, the stored polarization is destroyed, and the information is lost. Thus, a rewrite operation of the information is required. Since the rewrite operation is performed in every read operation, polarization reversal is repeatedly caused in every rewrite operation, resulting in fatigue and degradation of the polarization. In addition, since polarization charge is read by a sense amplifier in the structure, the amount of charge (typically 100 fC) needs to be at least the detection limit of the sense amplifier. Each ferroelectric material has unique polarization charge per unit area. Thus, even when miniaturizing memory cells, a certain electrode area is required as long as the same material is used. It is therefore difficult to reduce the capacitor size in proportion to the miniaturization of process rules, and the capacitor type ferroelectric memories are not suitable for increased capacitance.
In the FET type ferroelectric memories, however, information is read by detecting the conduction state of the channel that changes according to the polarization orientation of the ferroelectric film. This allows the information to be read in a non-destructive manner. Moreover, the amplitude of an output voltage can be increased by the amplifying operation of the FET, whereby miniaturization depending on the scaling law can be implemented. Conventionally, FET-type transistors have been proposed in which a ferroelectric film serving as a gate insulating film is formed on a silicon substrate serving as a channel. This structure is called a “metal-ferroelectric-semiconductor (MFS) FET.”
In a memory array having FET-type ferroelectric memories arranged in a matrix of rows and columns, an operation of writing binary data to the ferroelectric memory is performed by applying a voltage pulse between a gate electrode connected to a word line of a selected memory cell and a source electrode connected to a source line. However, at this time, the voltage is applied to those memory cells that are not to be accessed and are connected to the word line and the source line of the selected memory cell, causing erroneous writing of the data. Accordingly, a select switch, which is formed by, e.g., a metal-insulator-semiconductor FET (MISFET), is typically inserted between the word line and the gate electrode and/or between the source line and the source electrode to prevent such erroneous writing (see, e.g., Japanese Patent Publication No. H05-205487).
On the other hand, Japanese Patent Publication No. 2000-340759 proposes a NAND-type nonvolatile memory in which a gate electrode is provided on both surfaces of the semiconductor film, each memory cell is formed by a dual-gate transistor having a ferroelectric film connected to one of the gate portions, and the memory cells are connected in series as in flash memories.
FIG. 27 is a cross-sectional view showing a configuration of the memory cell described in Japanese Patent Publication No. 2000-340759. In a dual-gate transistor 100 forming a memory cell, a first gate electrode 105 is provided on one surface of a semiconductor film (a polycrystalline silicon film) 101 with both an insulating film 102 and a ferroelectric film 103 interposed therebetween, and a second gate electrode 106 is provided on the other surface of the semiconductor film 101 with an insulating film 104 interposed therebetween so that the second gate electrode 106 faces the first gate electrode 105. Source/drain regions (N-type silicon) 101b, 101b having an opposite conductivity type to a channel region (P-type silicon) 101a of the semiconductor film 101 are formed at both ends of the second gate electrode 106, respectively.